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# ANTIKERNEL v0.1                                                                                                      #
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# Copyright (c) 2012-2017 Andrew D. Zonenberg                                                                          #
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OledWideTestBitstream:

    # FPGA target using Xilinx tools (TODO: figure out how to do verilog/generic?)
    toolchain:      verilog/ise
    type:           bitstream

    # use default debug/release configs and flags

    # Specify target BSP rather than list of triplets
    boards:
        - ../../../bsp/zybo.yml

    # Signals that we need broken out at the top level
    pins:
        clk: 	1
        led: 	4
        switch: 4
        button: 4
        pmod_a:	8

    # Pull in GPU opcodes
    constants:
        ../../../antikernel-ipcores/graphics/gpu/Minimal2DGPU_opcodes.yml:
            - verilog/localparam

    # All source code for now, no automatic generation
    sources:
        - OledWideTestBitstream.v
        - ../../../antikernel-ipcores/clock/crossing/SwitchDebouncer.v
        - ../../../antikernel-ipcores/clock/crossing/SwitchDebouncerBlock.v
        - ../../../antikernel-ipcores/clock/crossing/ThreeStageSynchronizer.v
        - ../../../antikernel-ipcores/device_abstraction/ClockBuffer.v
        - ../../../antikernel-ipcores/device_abstraction/MemoryMacro.v
        - ../../../antikernel-ipcores/graphics/display/SSD1306.v
        - ../../../antikernel-ipcores/graphics/gpu/Minimal2DGPU.v
        - ../../../antikernel-ipcores/interface/spi/SPITransceiver.v
        - ../../../antikernel-ipcores/processor/zynq/XilinxZynq7CPU.v
