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# ANTIKERNEL v0.1                                                                                                      #
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# Copyright (c) 2012-2017 Andrew D. Zonenberg                                                                          #
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JtagBridgeTestBitstream:

    toolchain:      verilog/ise
    type:           bitstream

    # use default configs

    # Specify target BSP rather than list of triplets
    boards:
        - ../../../bsp/zybo.yml

    # Signals that we need broken out at the top level (in addition to anything that peripheral IP requires)
    pins:
        clk: 1
        led: 4

    # Pull in NoC address map
    constants:
        ../../../antikernel-ipcores/debug/JtagDebugBridge_addresses.yml:
            - verilog/localparam

    # All source code for now, no automatic generation
    sources:
        - JtagBridgeTestBitstream.v
        - ../../../antikernel-ipcores/clock/crossing/HandshakeSynchronizer.v
        - ../../../antikernel-ipcores/clock/crossing/ThreeStageSynchronizer.v
        - ../../../antikernel-ipcores/dataflow/CrossClockPacketFifo.v
        - ../../../antikernel-ipcores/debug/JtagDebugBridge.v
        - ../../../antikernel-ipcores/debug/JtagUserIdentifier.v
        - ../../../antikernel-ipcores/device_abstraction/ClockBuffer.v
        - ../../../antikernel-ipcores/device_abstraction/JtagTAP.v
        - ../../../antikernel-ipcores/math/CRC8_ATM.v
        - ../../../antikernel-ipcores/math/CRC32_Ethernet_x32.v
        - ../../../antikernel-ipcores/noc/rpcv3/RPCv3EchoNode.v
        - ../../../antikernel-ipcores/noc/rpcv3/RPCv3Transceiver.v
        - ../../../antikernel-ipcores/processor/zynq/XilinxZynq7CPU.v
